






			        

	   PDP11 -  


			*	*	*


		DESCRIPTION OF THE PDP11 COMMANDS


		  :
	*   -0  , 1  
	ss  -  (6 )
	dd  -  (6 )
	R   -   (3 )
	xx  - (8 ), +127 .. -128
	n   - (3 )
	M   - (4 )
	nn  -(6 )
	\   -/ 
	eis -EIS 
	fis -FIS 
	fpu -FPU 
	cis -CIS 
	src - - 
	dst - - 
	offset - 
	CC  -  (    )
	PC=R7= -  
	SP=R6= -  
	PSW -   
	?   -   MACRO-11 [61],   
	::  - - () 
	mmg -  
	si  - :    
	  :
	-   - 
	1   -   1
	0   - 
	*   -/     :
	     N -,     ,
		 ;
	     Z -   ,  ;
	     V -   ,  
		;
	     C -     ,  
		;
	+   -   -    .

	Last correction : Date 06/02/90  Time 01:42:08


op.	op.    instr.  PSW(CC)
code	name	set	NZVC	description

000000	HALT		----	           :
				           
				,  PC         
				  ,  PC       
				,   .   
				  :18011,2,3,
				1811          
				. 
				    18011     (177716)<-000010!(177716),
				(177676)<-(PSW),(177674)<-(PC),(PC)<-(160002)
				(PSW)<-(160004);
				 2       
				   HALT     ,
				    HALT    HALT,  
				     NOP.    
				:      ,  
				       
				DEC,  ,    
				      ,        
				             
				;      ,
				        KERNEL,  
				            
				KERNEL      ;      
				KERNEL  ,      
				1801/06 3.      HALT      KERNEL
				         HALT:    
				     100000
				           PC,    PSW;
				  PSW     340,    
				      
				22-     0 
				 (  ).

000001	WAIT		----	    .   
				         
				        

				.  PC        
				WAIT .       
				            
				  WAIT .

000002	RTI		++++	    .PC<-(SP)+,PSW<-(SP)+,
				         
				 :
				 18012   H        
				HALT        HALT    USER

000003	BPT		++++	          14    .
				-(SP)<-PSW,  -(SP)<-PC,  PC<-(14),  PSW<-(16)
				n,z,v,c:    

000004	IOT		++++	    -    20
				.  -(SP)<-PSW,  -(SP)<-PC,    PC<-(20),
				PSW<-(22);  n,z,v,c:        
				;       
				 - IOX    
				     
				   .

000005	RESET		----	      .    ,
				        ,        
				USER  /  SUPERVISOR        NOP.
				       
				 .       
				         .

000006	RTT	eis	++++	 RTI,       T
				 PSW         
				    .

000007	MFPT	?		  

000010	START	si	++++	18012        TRAP  TO  10,  
000011	START	si		halt  -    PC<-PC',PSW(8-0)<-PSW'(8-0),
000013	START	si		    IRQ,          
				 .     
				HALT->USER.

000012	START	si		    18012,   
				  18011:(177716)<-177767&(177716)
				(PC)<-(177674),	(PSW)<-(177676)

000014	STEP	si	----	18012        TRAP  TO  10,  
000015	STEP	si		halt -   PC<-PC',  PSW(8-0)<-PSW'(8-0),
000017	STEP	si		          
				  PC,   ,
				   HALT   .
000016	STEP	si		    18012,   
				  18011:(177716)<-177767&(177716)
				(PC)<-(177674), (PSW)<-(177676)
		
000020	RD	si	**--	18012   (    
				,          RPLY    )
				R0<-(SEL)    

000021	URD	si	**--	18012        USER: 
				R0<-(R5)+   halt- .

000022	RDPC	si	**--	18012    PC: R0<-PC',    
000023	RDPC	si		 .

000024	RDPS	si	**--	18012   PSW: R0<-PSW',   
000025	RDPS	si		 
000026	RDPS	si
000027	RDPS	si

000030	RD	si	**--	18012       
				000020

000031	UWR	si	**--	18012      USER:
				R0-> -(R5)    .

000032	WRPC	si	**--	18012    PC: R0->PC',   
000033	WRPC	si		 .

000034	WRPS	si	++++	18012    PSW: R0->PSW',   
000035	WRPS	si	****	  
000036	WRPS	si
000037	WRPS	si


00004:		\
00005:		\
00006:		\
00007:		\

0001dd	JMP		----
				.  PC    ,  
				  dd.      0    (
				  ,       
				  )        
				   TRAP TO  4;  PC<-(dst)

00020R	RTS		----	    . PC <- R, R <- (SP)

00021R		si	----	LSI-11:    
				16-    :       (R)<-(R)+12;
				     :
				(R): RBA  -      .  
				  ,     
				 ,     -
				   3,5,6,7; 
				(R)+2: RSRC  -      ,
				             
				   .        
				  0    
				;
				(R)+4: RDST -      -
				          ,
				 ;
				(R)+6: RPSW -  4   -    
				4 - 7   ,  -
				;
				(R)+10: RIR -    -  
				,      ,  
				  36R  -     .

00022n		si	----	LSI-11:    
				 3000;    ,
				   .


00023n	SPL	mmg	----	    .    
				  KERNEL:  PSW(5-7)<-n;       USER,
				SUPERVISOR   NOP.

000240	NOP		----	  ,     
				  PSW (M=0, . . ).

00024M	CL<NZVC>	++++	    PSW(N,Z,V,C)         4
				   .
000241	(CLN)			(M=^B1000)
000242	(CLZ)			(M=^B0100)
000244	(CLV)			(M=^B0010)
000250	(CLC)			(M=^B0001)
000257	(CCC)			(M=^B1111)

000260	NOP'		----	  ,   
				 ,   000240   ,
				       PSW
				(M=0, . . ).

00026M	SE<NZVC>	++++	  PSW(N,Z,V,C)    4
				   .
000261	(SEN)			(M=^B1000)
000262	(SEZ)			(M=^B0100)
000264	(SEV)			(M=^B0010)
000270	(SEC)			(M=^B0001)
000277	(SCC)			(M=^B1111)

0003dd	SWAB		++00	   :byte1/byte0<-byte0/byte1
				n,z           
				

0004xx	BR		----	 .  xx -
				   2,    n    PC:
				PC<-PC+(2*offset)

0010xx	BNE		----	   :  PC<-PC+(2*offset) if z=0

0014xx	BEQ		----	  :     PC<-PC+(2*offset) if z=1


0020xx	BGE		----	    :
				PC<-PC+(2*offset) if n xor v =0

0024xx	BLT		----	  :
				PC<-PC+(2*offset) if n xor v =1

0030xx	BGT		----	  :
				PC<-PC+(2*xx) if z!(n xor v) =0

0034xx	BLE		----	    :
				PC<-PC+(2*xx) if z!(n xor v) =1

004Rdd	JSR		----	  :      -(SP)<-R,R<-PC,
				PC<-(dst) 

*050dd	CLR(B)		0100	 : (dst)<-0

*051dd	COM(B)		**01	  :
				(dst)<-~(dst)

*052dd	INC(B)		**+-	  1    :  (dst)<-(dst)+1;
				v       (dst)    
				077777,  

*053dd	DEC(B)		**+-	  1    :   (dst)<-(dst)-1;
				v ,   (dst)    100000,
				 .

*054dd	NEG(B)		**++	            1
				(     ):    (dst)<-    -(dst);
				v ,    100000
				  ;  c       
				 0,  

*055dd	ADC(B)		**++	         (
				    ):        (dst)<-(dst)+c
				v ,  (dst)  077777   c
				 ,  ;
				c ,  (dst)  177777   c
				 ,  


*056dd	SBC(B)		**++	          (
				   ):   (dst)  <-  (dst) - c
				v=1  (dst)   100000,    ;
				c=1  (dst)   0,    c    

*057dd	TST(B)		**00	   PSW , 
				

*060dd	ROR(B)		**++	    :      
				     ;  
				     ,   , 
				   ,       
				; v=xor(c,n).

*061dd	ROL(B)		**++	    :       
				     ;   
				   ,   
				    ; v-xor(c,n).

*062dd	ASR(B)		**++	      :     
				       ;
				 ()     ;
				      
				;  v=xor(c,n).     
				    , 
				,    .

*063dd	ASL(B)		**++	      :    
				        ,
				   ,    
				   ;  v=xor(c,n). 
				            
				   2. 

0064nn	MARK		----	 :
				SP <- PC+2*nn,  PC<-R5,  R5<-(SP)+;  nn- 
				.

1064ss	MTPS		++++	   :  PS<-ss,    
				      .


0065ss	MFPI	mmg	**0-	        
				            
				 .

0066dd	MTPI	mmg	**0-	             
				        
				 .

1065ss	MFPD	mmg	**0-	        
				      
				.       
				   
				  ,  MFPI.

1066dd	MTPD	mmg	**0-	             
				            
				 .         
				           
				            , 
				    MTPI.

1067dd	MFPS			    : (dst)<-PSW;   
				       .

0067dd	SXT	eis	-+0-	 :
				(dst)<-0   n 
				(dst)<-177777   n 
				z ,   n 

0070dd	CSM	?

0071::		\

0072nn	TSTSET	?

0073nn	WRTLCK	?

0074::		\
0075::		\
0076::		\
0077::		\


*1ssdd	MOV(B)		**0-	: (dst)<-(src); MOVB ss,Rn 
				(         ),
				         ,
				           
				      ;    
				      
				        .     
				            
				    .

*2ssdd	CMP(B)		***+	 src  dst    
				PSW: (src) - (dst); 
				v=1,     ,   
				    ,     
				(     ) ;      
				c=0,         , 
				  .
				    .

*3ssdd	BIT(B)		**0-	    dst     src   
				 : (src)&(dst)

*4ssdd	BIC(B)		**0-	  dst   src:
				(dst)<-~(src)&(dst)

*5ssdd	BIS(B)		**0-	  dst   src:
				(dst)<-(src)!(dst)

06ssdd	ADD		****	dst<-src+dst;
				v ,    
				 ,   - ,
				 - 

16ssdd	SUB		***+	dst<-dst-src; 
				v  ,           
				  ,      
				,      ,   ;
				c  ,          
				,  - 


070Rss	MUL	eis	**0+	   ,  ,
				        -
				      
				 - ,   ( ) 
				,    -  
				.    , -
				    .

071Rss	DIV	eis	++++	32-    , 
				   Rn, R(n+1),  
				   - .  
				  ,    
				   .    
				 .
				n ,   
				,  ; z 
				,   ,  
				; v ,   
				()  ,    
				      
				:      
				,    
				 . c ,  
				  ,  .

072Rss	ASH	eis	**++	     
				   ,   - 
				.    6 
				  .   
				    , 
				 - .    
				  ,   - 
				  . v , 
				      
				,  ; c  
				 ,   . 

073Rss	ASHC	eis	**++	 ,    , 
				      
				 ,   

				 32 -  ,     
				    ,   
				   - ,   
				    ,   
				 .    
				 6   - . 
				    
				 ,  - .  
				  -  ,  
				  . 16- 
				     , 
				   .   
				   ,  
				     .
				v ,     
				 ,  ; c  
				   32-  
				.

074Rdd	XOR	eis	**0-	 '': (dst)<- R xor (dst)

07500R	FADD	fis	**00	initial state:
				R=>	operand B bits 16-31
					operand B bits 0-15
					operand A bits 16-31
				(R)+6=>	operand A bits 0-15
				After operation floating point stack
				looks:
				R=>
					operand B bits 16-31
					operand B bits 0-15
					result bits 16-31
					result bits 0-15
				result=A+B

07501R	FSUB	fis	**00	initial state:
				R=>	operand B bits 16-31
					operand B bits 0-15
					operand A bits 16-31
				(R)+6=>	operand A bits 0-15
				After operation floating point stack

				looks:
				R=>	operand B bits 16-31
					operand B bits 0-15
					result bits 16-31

					result bits 0-15
				result=A-B

07502R	FMUL	fis	**00	initial state:
				R=>	operand B bits 16-31
					operand B bits 0-15
					operand A bits 16-31
				(R)+6=>	operand A bits 0-15
				After operation floating point stack
				looks:
				R=>	operand B bits 16-31
					operand B bits
					result bits 16-31
					result bits 0-15
				result=A*B
				if the result <2E-128 then the result 
				is treated as zero.

07503R	FDIV	fis	**00	initial state:
				R=>	operand B bits 16-31
					operand B bits 0-15
					operand A bits 16-31
				(R)+6=>	operand A bits 0-15
				After operation floating point stack
				looks:
				R=>	operand B bits
					operand B bits
					result bits 16-31
					result bits 0-15
				result=A/B
				if the result <2E-128 then the result 
				is treated as zero.

07504:		\
07505:		\
07506:		\

07507:		\

076020	L2D0	cis

076021	L2D1	cis

076022	L2D2	cis

076023	L2D3	cis

076024	L2D4	cis

076025	L2D5	cis

076026	L2D6	cis

076027	L2D7	cis

076030	MOVC	cis

076130	MOVCI	cis

076031	MOVRC	cis

076131	MOVRCI	cis

076032	MOVTC	cis

076132	MOVTCI	cis

076033		\
076133		\
076034		\
076134		\
076035		\
076135		\
076036		\
076136		\
076037		\
076137		\


076040	LOCC	cis

076140	LOCCI	cis

076041	SKPC	cis

076141	SKPCI	cis

076042	SCANC	cis

076142	SCANCI	cis

076043	SPANC	cis

076143	SPANCI	cis

076044	CMPC	cis

076144	CMPCI	cis

076045	MATC	cis

076145	MATCI	cis

076046		\
076146		\
076047		\
076147		\

076050	ADDN	cis

076150	ADDNI	cis

076051	SUBN	cis

076151	SUBNI	cis

076052	CMPN	cis

076152	CMPNI	cis


076053	CVTNL	cis

076153	CVTNLI	cis

076054	CVTPN	cis

076154	CVTPNI	cis

076055	CVTNP	cis

076155	CVTNPI	cis

076056	ASHN	cis

076156	ASHNI	cis

076057	CVTLN	cis

076157	CVTLNI	cis

076060	L3D0	cis

076061	L3D1	cis

076062	L3D2	cis

076063	L3D3	cis

076064	L3D4	cis

076065	L3D5	cis

076066	L3D6	cis

076067	L3D7	cis

076070	ADDP	cis

076170	ADDPI	cis

076071	SUBP	cis


076171	SUBPI	cis

076072	CMPP	cis

076172	CMPPI	cis

076073	CVTPL	cis

076173	CVTPLI	cis

076074	MULP	cis

076174	MULPI	cis

076075	DIVP	cis

076175	DIVPI	cis

076076	ASHP	cis

076176	ASHPI	cis

076077	CVTLP	cis

076177	CVTLPI	cis

0762::		\
0763::		\
0764::		\
0765::		\

076600	MED6X	cis?

076601	MED74C	cis?

076602		\
076603		\
076604		\
076605		\
076606		\

076607		\
07661:		\
07662:		\
07663:		\
07664:		\
07665:		\
07666:		\

077Rnn	SOB	eis	----	R<-R-1;   0,  PC<- PC-2*offset

1000xx	BPL		----	,  :
				PC<-PC+(2*offset) if n=0

1004xx	BMI		----	, :
				PC<-PC+(2*offset) if n=1

1010xx	BHI		----	,  :
				PC<-PC+(2*offset) if c=0 & z=0

1014xx	BLOS		----	,   :
				PC<-PC+(2*offset) if c!z=1

1020xx	BVC		----	,  :
				PC<-PC+(2*offset) if v=0

1024xx	BVS		----	, :
				PC<-PC+(2*offset) if v=1

1030xx	BCC		----	,    :
1030xx	BHIS
				PC<-PC+(2*offset) if c=0

1034xx	BCS		----	,  :
1034xx	BLO
				PC<-PC+(2*offset) if c=1

1040::	EMT		++++	-(SP)<-PSW; -(SP)<-PC; PC<-(30); PSW<-(32)
1041::	EMT			n,z,v,c:    
1042::	EMT
1043::	EMT


1044::	TRAP		++++	-(SP)<-PSW; -(SP)<-PC; PC<-(34); PSW<-(36)
1045::	TRAP			n,z,v,c:    
1046::	TRAP
1047::	TRAP

107:::		\

code	name	       fpp(cc)	description
		      F(NZVC)

170000	CFCC	fpu

170001	SETF	fpu

170002	SETI	fpu

170003	LDUB	fpu

170004	LDSC	fpu

170005	STA0	fpu

170006	STB0	fpu

170007	STQ0	fpu

170010		\

170011	SETD	fpu

170012	SETL	fpu

170013		\

170014		\

170015		\

170016		\

170017		\


1701SS	LDFPS	fpu

1702DD	STFPS	fpu

1703DD	STST	fpu

1704DD	CLRD	fpu
1704DD	CLRF	fpu

1705SS	TSTD	fpu
1705SS	TSTF	fpu

1706DD	ABSD	fpu
1706DD	ABSF	fpu

1707DD	NEGD	fpu
1707DD	NEGF	fpu

1710DD	MULD	fpu
1710DD	MULF	fpu

1714DD	MODD	fpu
1714DD	MODF	fpu

1720SDD	ADDD	fpu	***0	SUM=(AC)+(FSRC): if underflow occurs and FIU 
1720SDD	ADDF	fpu		is not enabled, AC<-exact 0
				if overflow occurs and FIV is not enabled,
				AC<-exact 0 on FP11C
				for all other cases, AC<-SUM
				The addition is carried out in single or 
				double precision and is rounded or chopped
				in accordance with the values of the FD and 
				FT bits in the FPS register. The result is 
				stored in AC except for:
				oerflow with interrupt disabled on the FP11C
				underflow with interrupt disabled.
				For these exceptional cases, an exact 0 is
				stored in AC.
				If FIVU is enabled, trap on -0 in FSRC
				occurs before execution.

				If overflow or underflow occurs and if the
				corresponding interrupt is enabled, the trap 
				occurs with the faulty result in AC. The 
				fractional parts are correctly stored.
				The exponent part is too large by 400 octal
				for underflow, except for the special case
				of 0, which is correct. If no errors occures,
				then for oppositely signed operands with
				exponent differences of 0 or 1, the answer
				returned is exact if a loss of significance
				of one or more bits occurs. Note that these
				are the only cases for which loss of 
				significance of more than one bit can occur.
				For all other cases the result is inexact 
				with error bounds of
				1 LSB in chopping mode with either single or 
				double precision.
				1/2 LSB in rounding mode with single 
				precision.
				9/16 LSB in rounding mode with double 
				precision.
				The undefined variable -0 can occur only in 
				conjunction with overflow or underflow.
				It will be stored in AC only if the 
				corresponding interrupt is enabled or, for 
				the FP11B, on overflow even if the overflow
				interrupt is not enabled.

1724SDD	LDD	fpu	**00	AC<-(FSRC)
1724SDD	LDF	fpu		load single or double precision number
				into accumulator. If FIVU is enabled,
				trap on -0g mode with single 
				precision.
				9/16 LSB in rounding mode with double 
				precision.
				The undefined variable -0 can occur only in 
				conjunction with overflow or underflow.
				It will be stored in AC only if the 
				corresponding interrupt is enabled or, for 
				the FP11B, on overflow even if the overflow
				interrupt is not enabled.

1724SDD	LDD	fpu	**00	AC<-(FSRC)
1724SDD	LDF	fpu		load single or double precision number
				into accumulator. If FIVU is enabled,
				trap on -0r.
				The result is stored in AC except for:
				  Overflow with interrupt disabled on the 
				  FP11C.
				  Underflow with interrupt disabled.
				For these exceptional cases, an exact 0 is 
				stored in AC.
				If FIUV is enabled, trap on -0 in FSRC occurs
				before execution. If overflow or underflow 
				occurs and if the corresponding interrupt is 
				enabled, the trap occurs with the faulty 
				results in AC. The fractional parts are 
				correctly stored. The exponent part is too 
				small by 400 octal for overflow. It is too 
				large by 400 octal for underflow, except for
				the special case of 0, which is correct.
				Errors due to overflow and underflow are 
				described above. If neither occurs, then: 
				For like-signed operands with exponent 

1734SDD	CMPD	fpu
1734SDD	CMPF	fpu

1740SDD	STD	fpu	----	FDST<-(AC): store single or double number
1740SDD	STF	fpu		from accumulator.

1744SDD	DIVD	fpu
1744SDD	DIVF	fpu

1750SDD	STEXP	fpu

1754SDD	STCDI	fpu
1754SDD	STCDL	fpu
1754SDD	STCFI	fpu
1754SDD	STCFL	fpu

1760SDD	STCDF	fpu
1760SDD	STCFD	fpu

1764SDD	LDEXP	fpu


1770SDD	LDCID	fpu
1770SDD	LDCIF	fpu
1770SDD	LDCLD	fpu
1770SDD	LDCLF	fpu

1774SDD	LDCFD	fpu
1774SDD	LDCDF	fpu
